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ATmega128
16-bit
Timer/Counter
Register
Description
Timer/Counter1
Control Register A –
Bit
7
6
5
4
3
2
1
0
TCCR1A
Read/ W rite
Initial Value
COM1A1
R/ W
0
COM1A0
R/ W
0
COM1B1
R/ W
0
COM1B0
R/ W
0
COM1C1
R/ W
0
COM1C0
R/ W
0
WGM11
R/ W
0
WGM10
R/ W
0
TCCR1A
Timer/Counter3
Control Register A –
Bit
7
6
5
4
3
2
1
0
TCCR3A
Read/ W rite
Initial Value
COM3A1
R/ W
0
COM3A0
R/ W
0
COM3B1
R/ W
0
COM3B0
R/ W
0
COM3C1
R/ W
0
COM3C0
R/ W
0
WGM31
R/ W
0
WGM30
R/ W
0
TCCR3A
? Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
? Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
? Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
W hen the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the W GMn3:0 bits setting. Table 58 shows the COMnx1:0 bit functionality when
the W GMn3:0 bits are set to a normal or a CTC mode (non-P W M).
Table 58. Compare Output Mode, non-P W M
COMnA1/COMnB1/
COMnA0/COMnB0/
COMnC1
0
0
1
1
COMnC0
0
1
0
1
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on compare
match.
Clear OCnA/OCnB/OCnC on compare
match (set output to low level).
Set OCnA/OCnB/OCnC on compare match
(set output to high level).
132
2467X–AVR–06/11
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